This invention pertains to solid-state image-pickup devices and associated drive-signal timing methods. Such solid-state image-pickup devices comprise a plurality of light-sensitive pixels arranged in a planar array and output a video signal corresponding to the image sensed by the pixels. In particular, this invention pertains to solid-state image-pickup devices that produce video signals with improved video-frame processing rates.
Solid-state image-pickup devices are typically used in electronic camera equipment such as camcorders and digital still cameras. These devices measure light intensity at multiple discreet locations on a plane to image a scene. The devices contain an array of pixels that convert light intensity into measurable voltage signals. These voltage signals are then processed to produce a video output signal that may be stored or viewed on a video display.
Until recently, solid-state image-pickup devices provided relatively low display resolutions and generally comprised 100,000 pixels or less. More contemporary solid-state image-pickup devices have much higher resolutions, with the most recent devices employing 300,000 to 1,000,000 pixels.
While higher-resolution imaging devices are desirable, they have the drawback of requiring more signal processing to produce each frame of video output signal. This additional signal processing often results in an undesirable time-lag between the sensing and display of the image. If the imaged subject (such as a person) is moving, the time-lag may cause the displayed image (as viewed by the operator of the camera equipment) to have an inaccurate sense of what is happening in real time. This is especially a concern with digital still cameras, because if the image displayed on the viewfinder is not in real time, the camera operator will not be certain of the picture that will result when the camera shutter is actuated.
Consider a case in which a video image is displayed on the small electronic viewfinder of a camcorder or digital still camera. If the photographic subject is moving, the image displayed on the viewfinder must be updated, or xe2x80x9crefreshed,xe2x80x9d frequently to smoothly (and accurately) display the photographic subject. Each refresh comprises outputting a new xe2x80x9cframexe2x80x9d of video information to the viewfinder. The updating frequency directly affects how smoothly and accurately the photographic subject is displayed; higher refresh rates provide for smoother displays of motion. For example, the film industry uses a refresh rate of 24 frames per second, and a television screen is typically updated at 30 frames per second. Both of these frame rates provide smooth flicker-free viewing for most people.
As the number of pixels in a solid-state image-pickup device increases, the time to refresh each frame necessarily increases. This is because the processing and display of each pixel requires a finite amount of time; the more pixels to process, the more time required. Images directly displayed from many types of conventional high-resolution solid-state image-pickup devices often exhibit prohibitively slow frame-updating speeds. It is then necessary to provide additional video processing measures, such as decreasing the number of pixels in the video signal, to provide adequate frame-updating speeds.
An additional problem inherent in the use of conventional solid-state image-pickup devices pertains to displaying video output on monitors or viewfinders that have a different pixel aspect ratio than that of the solid-state image-pickup device. For instance, a standard television has a display resolution of 755 horizontalxc3x97484 vertical pixels, which equates to an aspect ratio of 755/484 (approximately 1.6). Since the output signals from many solid-state image-pickup devices are designed to be shown on a standard television screen, these devices typically have aspect ratios close to 1.6. In contrast, many camcorder or camera viewfinders are approximately square in shape, which equates to a pixel aspect ratio of about 1.
In general, when a solid-state image-pickup device and a video display have different aspect ratios, the displayed video image will be distorted either lengthwise or width-wise. A solution to this undesirable effect is to perform additional video processing, such as adjusting the number of horizontal and/or vertical pixels in the video signal.
While additional video processing may solve the frame-updating and aspect-ratio problems, it is not the most desirable solution. Additional video processing increases the overall circuit complexity and cost, since such processing typically requires frame memory and/or subtraction circuits, etc. The additional processing steps also result in diminished frame-refresh rates.
One method for improving the screen-refresh rate is to simultaneously read-out the dark and output signals for respective horizontal lines of pixels in a continual sequential fashion. A solid-state image-pickup device that employs this technique is disclosed in Japan Kxc3x4kai Patent Document No. SHO 62-128679.
FIG. 21 schematically shows an example of an electrical circuit configuration of a solid-state image-pickup device that simultaneously reads out the dark and output signals, one horizontal line of pixels at a time.
In FIG. 21, multiple pixels 80 are arranged in a planar array of columns and rows. Each pixel 80 comprises a photodiode 81 to perform photoelectric conversion, a JFET (junction-type field-effect transistor) 82 to current-amplify the charge accumulated by the photodiode 81, a MOS switch 83 to shift the charge accumulated by the photodiode 81 to the gate electrode of the JFET 82, and a MOS switch 84 to initialize the gate potential of the JFET 82.
The gate electrodes of the MOS switches 83 are commonly connected in each horizontal line of the pixel array. Each of these horizontal lines is individually connected to respective control pulses "PHgr"TG1, "PHgr"TG2, . . . ("PHgr"TG1 connected to the first horizontal line, "PHgr"TG2 connected to the second horizontal line, etc.) that are output from a vertical scanning circuit 87.
Similarly, for a given horizontal line of pixels, the MOS switches 84 are commonly connected, with each line individually supplied with a respective control potential "PHgr"RSD1, "PHgr"RSD2, . . . , which is output from the vertical scanning circuit 87. In addition, the gate electrodes of the MOS switches 84 are commonly connected throughout the entire pixel array and are supplied with a control pulse "PHgr"RSG.
The source electrodes of the JFETs 82 are commonly connected in each vertical column of pixels to respective vertical read-out lines 85. A reset MOS switch 85a and constant current source 86 are respectively connected to each of the vertical read-out lines 85. The gate electrodes of all the MOS switches 85a are commonly connected and are supplied with a control pulse "PHgr"RSTV.
The output terminal of each vertical read-out line is connected to a pair of MOS switches 88s, 88d. The gate electrodes of the MOS switches 88s are all commonly connected and supplied with a control pulse "PHgr"Ts. The gate electrodes of the MOS switches 88d are also all commonly connected and supplied with a control pulse "PHgr"Td. Collectively, these MOS switches and control lines form a multiplexer circuit.
Capacitors 89s, 89d are respectively connected to the output terminals of the MOS switches 88s, 88d. By following each vertical read-out line 85 upward it can be seen that a respective pair of capacitors 89s, 89d is provided for each vertical read-out line 85; thus, these capacitors are marked 89s2, 89d2 (corresponding to the first vertical read-out line), 89s2, 89d2 (corresponding to the second vertical read-out line), etc.
Two capacitors for each vertical read-out line are provided because of the pixel-output variances associated with solid-state image-pickup devices. Each pixel in the array produces a voltage output that depends on the light intensity sensed by the pixel. In the ideal case the output of each pixel would be identical (for equal light intensities), and the pixels would produce zero output when in complete darkness. However, the pixels in actual devices still produce an output, known as a dark signal, when they receive zero light. To make matters worse, the dark signal produced by each of the pixels varies. This variance in pixel output that occurs when the array receives no light is called the xe2x80x9cfixed-pattern noise.xe2x80x9d Other forms of fixed-pattern noise (such as that associated with the pixel support circuitry) may be caused by synchronous-timing-generation effects at high data rates.
A method to reduce the effect of the fixed pattern noise is to measure the difference between the output signal and the dark signal for each pixel. Thus, a separate pair of capacitors, one to accumulate the output signal, and the other to accumulate the dark signal, are provided for each vertical read-out line. This provides a means of separately accumulating the pixel output from each horizontal line. The group represented by the capacitors 89s1xe2x88x9289sn accumulates the pixel output signals (via the JFETs 82) in horizontal line units (that is, the output signals of all the pixels in a selected horizontal line are accumulated at one time). Similarly, the group represented by the capacitors 89d1xe2x88x9289d accumulates the dark (reference) signals for each pixel in horizontal line units.
The charges stored in the capacitors 89s, 89d need to be sequentially output to horizontal read-out lines. To accomplish this, each of the capacitors 89s, 89d is respectively connected to a horizontal read-out line 91s, 91d via individual horizontal scanning MOS switches 90s, 90d. As with the capacitors 89s, 89d, the MOS switches 90s1, 90d1 correspond to the first vertical read-out line, the MOS switches 90s2, 90d2 to the second vertical read-out line, etc.
The gate electrodes of each pair of MOS switches 90s, 90d commonly connected to a respective vertical read-out line 85 are supplied a respective control pulse "PHgr"H1, "PHgr"H2, . . . output from a shift register circuit 92 (i.e., control pulse "PHgr"H2 is supplied to the gate electrodes of the MOS switches 90s1, 90d1, control pulse "PHgr"H2 is supplied to the gate electrodes of the MOS switches 90s2, 90d2, etc.). A start pulse and two clock pulses "PHgr"CK1, "PHgr"CK2 are respectively supplied to this shift register circuit 92.
MOS switches 96s, 96d for resetting the residual charges remaining in the read-out lines 91s, 91d, and capacitors 89s, 89d are respectively connected to the horizontal read-out lines 91s, 91d. The gate electrodes of the MOS switches 96s, 96d are commonly supplied a reset control pulse "PHgr"RSTH.
FIG. 22 is a pulse chart showing the drive timing for the FIG.-21 device. The read-out operation of the solid-state image-pickup device will be explained below, with reference to this figure.
At the start of timing period T1, "PHgr"RSD1 is switched to a high-potential bias voltage while "PHgr"RSG is held at low potential. This initializes the gate potentials of the JFETs 82 in the first row of pixels 80 (row 1) to a desired bias potential, while the gate electrodes of the remaining JFETs 82 (those not in row 1) are held at low potential by means of "PHgr"RSD2, "PHgr"RSD3, . . . (which remain low).
Just prior to the start of timing period T2, "PHgr"Td1 is switched to high potential, followed by "PHgr"RSTV being switched to low potential. As a result, the source follower output of the JFETs 82 in row 1 charges the capacitors 89d via the MOS switches 88d. By this operation, the dark signals generated by the pixels in the first row are respectively accumulated in the group of capacitors 89d. 
Next, "PHgr"TG1 is switched to low potential at the start of timing period T3. As a result, the signal charges that have been photoelectrically converted by the photodiodes 81 in row 1 are shifted to the gate electrodes of the JFETs 82 via the MOS switches 83.
Just prior to the start of timing period T4, "PHgr"Ts1 is switched to high potential, followed by "PHgr"RSTV being switched to low potential. At this point the source follower output of the JFETs 82 in row 1 charges the capacitors 89s via the MOS switches 88s. This results in the output signals generated by the pixels in the first row being respectively accumulated in the group of capacitors 89s. 
The first vertical read-out operation of the first row of pixels is completed by the above series of operations (T1-T4).
Immediately following this first vertical read-out period, as identified by timing period T90, a start pulse is supplied to the shift register circuit 92. When this occurs, the control pulses "PHgr"H1, "PHgr"H2, . . . of the shift register circuit 92 are sequentially set to high potential according to the two shift clocks "PHgr"CK1, "PHgr"CK2.
As a result, the signal generated by the pixels in the first row, which has accumulated in capacitors 89s, 89d, is horizontally scanned one pixel at a time by the MOS switches 90s, 90d, and sequentially read out to the horizontal read-out lines 91s, 91d. Thus, the signal of the first row of pixels is output from the horizontal read-out lines 91s, 91d as video signals Vos, Vod.
The residual charges in the horizontal read-out lines 91s, 91d and capacitors 89s and 89d must be removed between the scanning of each horizontal line in preparation for the next pixel read-out. This xe2x80x9cresetxe2x80x9d is accomplished by momentarily providing a path to ground for the residual charges in each read-out line and in the most-recently scanned capacitors. This is accomplished by momentarily switching "PHgr"RSTH to high potential just prior to the respective rise of "PHgr"H1, "PHgr"H2, . . . , as shown in FIG. 22. As a result, in preparation for the next pixel read-out, the residual charges in the horizontal read-out lines 91s, 91d and the residual charges in the capacitors 89s, 89d that have been most-recently scanned are discharged to ground, thereby resetting the horizontal read-out lines 91s, 91d for the next pixel read-out and resetting the most recently scanned capacitors 89s, 89d for the next vertical read-out operation.
A video signal is produced by an external processing circuit (not shown) by measuring the difference between the video signals Vos, Vod, thereby removing the dark signal output (fixed-pattern noise).
A frame of video signal can be read out by repeating the above horizontal line read-out process while shifting the position of the horizontal line being read out in the vertical direction.
A limitation with the conventional device summarized above is that it cannot read out multiple rows of pixels at a time, which is another technique for enhancing screen-refresh rates.
A solid-state image-pickup device that simultaneously outputs a pair of horizontal lines is disclosed in Japan Kxc3x4kai Patent Document No. HEI 1-154678. FIG. 23 is a schematic block diagram corresponding to a conventional solid-state pickup device that can simultaneously read out multiple rows of pixel output. In FIG. 23, multiple pixels 61 are arranged in a planar array of columns and rows on the light-receiving surface of a solid-state image-pickup device. These pixels are similar to those described above. Each vertical column of pixels 61 is commonly connected to a vertical read-out line 62.
The pixels 61 and vertical read-out lines 62 are interconnected by MOS switches 63a. In each row of pixels the gate electrode of each of the MOS switches 63a is connected to a respective horizontal line. The horizontal lines are connected to respective control outputs of a shift register 63b. 
The outputs of the vertical read-out lines 62 are input to a multiplexer 64. Respective horizontal accumulators 65a, 65b, each accumulating the output of one row of pixels, are provided for each output destination of the multiplexer 64. The horizontal accumulators 65a, 65b are driven by a single horizontal scanner 66.
The output timing of the video signal from the FIG.-23 device is schematically depicted in FIG. 24.
In a first vertical read-out period (FIG. 24), the shift register 63b sets all of the MOS switches 63a in the nth horizontal line to the ON state, and the signal charges generated by the pixels 61 of the nth horizontal line are input to the multiplexer 64 via the vertical read-out lines 62. The multiplexer 64 outputs the nth horizontal line signal to the horizontal accumulator 65a, where the signal is accumulated without alteration.
In the second vertical read-out period, the shift register 63b sets all of the MOS switches 63a in the mth horizontal line to the ON state, and the signal charges generated by the pixels 61 in the mth horizontal line are input to the multiplexer 64 via the vertical read-out lines 62. The multiplexer 64 outputs the mth horizontal line signal to the horizontal accumulator 65b, where the signal is accumulated without alteration.
After both horizontal accumulators 65a and 65b are loaded, they are driven in parallel by horizontal scanner 66 to simultaneously horizontally shift the nth horizontal line and mth horizontal line signals out as video signals Vos1 and Vos2, respectively. Thus, it is possible with the FIG.-23 device to read-out the signals of two horizontal lines during a single horizontal read-out period.
However, with the FIG.-23 device, no video signals can be output during the entire time frame comprising the first and second vertical read-out periods. Operation of the horizontal accumulator 65b is stopped (it receives no input and provides no output) during the first vertical read-out period, as shown in FIG. 24. Similarly, operation of the horizontal accumulator 65a is stopped during the second vertical read-out period. These idle periods are repeated for every pair of horizontal lines being read out. As a result, the idle periods significantly reduce the frame-refresh speed of the FIG.-23 device.
In view of the foregoing shortcomings of conventional devices, an object of this invention is to provide a solid-state image-pickup device that produces a video signal with improved screen-refresh rates. Another object of this invention is to provide a solid-state image-pickup device that produces a video signal that can be directly displayed on a video screen without requiring additional video processing.
The invention is exemplified by several device embodiments that accomplish the foregoing objects by simultaneously combining the pixel output signals from adjacent pixels and reading out the combined output signals to produce a video signal, and/or by simultaneously reading out the output signals from multiple horizontal lines of pixels to produce a video signal.
According to one aspect of the invention, solid-state image-pickup devices are provided that comprise multiple pixels arranged in a planar array of columns and rows, each pixel producing an electrical output signal according to a light quantity received by the pixel.
According to a first representative embodiment, a separate vertical read-out line is provided for each column of pixels, with the outputs of each pixel in a respective column commonly connected to a respective vertical read-out line. Each vertical read-out line has an output terminus. Control inputs for triggering the pixel outputs are commonly connected by row to respective control signal lines output from a vertical scanning circuit. The vertical scanning circuit controllably switches the outputs of the multiple pixels in each column to the vertical read-out lines according to a predetermined horizontal-line read-out sequence. The vertical read-out line output termini are connected to a multiplexer that distributes the pixel output signals carried by the vertical read-out lines to multiple selected multiplexer outputs. A horizontal accumulator is connected to the multiplexer outputs and temporarily accumulates the respective pixel output signals output from the multiplexer for delivery to horizontal accumulator outputs. The horizontal accumulator outputs are connected to horizontal read-out lines. The device further comprises horizontal scanning means for controllably triggering pixel output signals temporarily accumulated in the horizontal accumulator for sequential read-out onto the horizontal read-out lines to form a video signal. The device components are driven so-as to simultaneously combine the output signals from adjacent pixels to produce a video signal. The combined pixel-output signals can be made from N (where Nxe2x89xa72) horizontally adjacent pixels, M (where Mxe2x89xa72) vertically adjacent pixels, or (N horizontalxc3x97M vertical) adjacent pixels.
According to a second representative embodiment, the solid-state image-pickup device can comprise red (R), green (G), and blue (B) filters arranged in a Bayer array sequence above the pixels. According to the arrangement of the filters, the pixels are grouped by R, G, and B color designators such that no two horizontally or vertically adjacent pixels share the same designator. The pixels designated with a G are diagonally connected throughout the array, with the remaining pixels designated by alternating rows of R and B. The combined output signals from M (where Mxe2x89xa72) vertically adjacent pixels that share the same color designator can be sequentially read-out with this device. Alternately, the combined output signals from N (where Nxe2x89xa72) horizontally adjacent pixels that share the same color designator can be sequentially read-out with this device.
According to a third representative embodiment, a solid-state image-pickup device is provided comprising multiple horizontal accumulators and multiple respective horizontal scanning circuits. Each horizontal scanning circuit individually drives a respective horizontal accumulator to sequentially read out the accumulated pixel output signals stored in each horizontal accumulator to form a video signal. The output signals from M (where Mxe2x89xa71) horizontal lines of pixels are divided and stored in the horizontal accumulators. The horizontal accumulators can be individually driven by respective horizontal scanning circuits to horizontally shift the output signals from M horizontal lines of pixels in parallel to the horizontal read-out lines.
Each of the pixels in any of various embodiments of the invention preferably comprises a respective photodiode for performing photoelectric conversion of the light quantity received by the pixel, a respective JFET (junction-type field-effect transistor) for amplifying the current of the charge accumulated in the respective photodiode, a respective MOS switch for shifting the charge accumulated in the respective photodiode to the gate electrode of the respective JFET, and a respective MOS switch that has an electrode connected to the gate of the respective JFET for initializing the gate potential of the JFET.
The multiplexer preferably comprises multiple MOS switches and a set of control lines. The MOS switches are preferably grouped in units of two or four, with a group of MOS switches connected to each vertical read-out line. The number of control lines preferably matches the number of MOS switches in a group. The gate electrodes of the MOS switches in a group are preferably individually connected to respective control lines.
The horizontal accumulator preferably comprises multiple groups of capacitors (one group for each vertical read-out line), a respective MOS switch for each capacitor, and control lines connected to the gate electrodes of the respective MOS switches. Preferably two or four capacitors are provided in each group, although this is not meant to be limiting. The gate electrodes of the MOS switches are preferably commonly connected in pairs to respective control lines.
The horizontal scanning means preferably comprises a horizontal shift register and one or more horizontal selection circuits. The horizontal scanning means provides timing signals to the control lines of the horizontal accumulator to sequentially connect the capacitors in the horizontal accumulator to the horizontal read-out lines.
The foregoing and additional features and advantages of the invention will be more readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings.